1. Field of the Invention
This invention relates to logic circuits for symmetrically dividing an input frequency by an odd modulus.
2. History of the Prior Art
Frequency dividing circuits produce signals that are symmetrical or asymmetrical. The symmetrical signal is one which has a duty cycle of substantially 50%. In other words, for a sqaure wave or logic signal, the duration of the signal indicating a logical one is substantially equivalent to the duration of the signal designating a logical zero. Digital circuits are especially applicable to dividing circuits because of devices such as clocked flip-flops and gating circuits.
When the modulus of division is even, the output waveform is usually symmetrical. When the modulus of division is odd, however, the output signal is usually asymmetrical if the design objective is to keep the associated circuit as simple as possible.
In countdown circuits where the portion of the signal that is most important is the leading or falling edge of the signal, an asymmetrical signal will perform satisfactorily. Some applications, however, notably in communications work, require symmetrical waveforms which contain fewer harmonics in a given bandwidth. This increases the power in the frequency of interest, usually extracted by filters. A symmetrical square output waveform consists only of odd harmonics so that less complex filters are required. The output signal from some odd modulus dividers contain transients, which result from finite rise and fall times as well as inherent circuit delays.
This disclosure describes an invention which produces a substantially symmetrical output signal in an odd modulus divider circuit without producing the undesirable transients described above even when the frequency of the input signals is nearly equal to the reciprocal of the delay through various stages.